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Last Update5/15/2021 |
I am a Principal Engineer in AI Research at Qualcomm, specializing in advancing computer architecture and memory systems. My work emphasizes creating energy-efficient solutions tailored for future computer systems and AI workloads. Previously, I served as an Assistant Professor at the University of Utah’s School of Computing, where I led research initiatives and contributed to developing innovative technologies in computing.
My research lies at the intersection of computer architecture, memory systems, and energy-efficient computing. I am particularly interested in designing architectures that support sustainable and high-performance computing for AI and next-generation workloads.
Honors and Awards
- Dean's teaching commendation letter for Advanced Computer Architecture (CS/ECE 7810), 2017
- IEEE Micro Top Picks in Computer Architecture, 2017
- HPCA Distinguished Paper Award, 2016
- IEEE Micro Top Picks in Computer Architecture, 2013
- Samsung Best Paper Award, 2012
Selected Publications (see all publications)
- FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-Signal DNN Accelerator, ISCA, 2021
- Memristive Data Ranking, HPCA, 2021
- G-Arrays: Geometric Arrays for Efficient Point Cloud Processing, ICASSP, 2021
- STFL-DDR: Improving the Energy-Efficiency of Memory Interface, IEEE TC, 2020
☆ Featured Paper of the Month - December 2020. - RedCache: Reduced DRAM Caching, DAC, 2020
- ReTagger: An Efficient Controller for DRAM Cache Architectures, DAC, 2019
- STFL: Energy-Efficient Cache Interface using Slow Transition Fast Level Signaling, DAC, 2019
- Accelerating k-Medians Clustering using a Novel 4T-4R RRAM Cell, TVLSI, 2018
- Memristive Boltzmann Machine: A Hardware Accelerator for Combinatorial Optimization and Deep Learning, HPCA, 2016
☆ IEEE Micro Top Picks; ☆ Distinguished Paper Award. - Enabling Energy Efficient Hybrid Memory Cube Systems with Erasure Codes, ISLPED, 2015
✐ Highlighted by The Next Platform (here). - DESC: Energy-Efficient Data Exchange using Synchronized Counters, MICRO, 2013
- PARDIS: A Programmable Memory Controller for the DDRx Interfacing Standards, ISCA, 2012
☆ IEEE Micro Top Picks; ☆ Invited paper for publication in ACM TOCS.
Teaching
- CS/ECE 3810: Computer Organization (Fall 2020, Spring 2019)
- CS/ECE 6810: Computer Architecture (Fall 2019, Fall 2018, Spring 2018, Fall 2016)
- CS/ECE 7810: Advanced Computer Architecture (Spring 2021, Spring 2020, Spring 2017)
- CS 7937: Architecture and VLSI Seminar (Fall 2017-Spring 2021)
Students
Graduated
- Manikanth Miryala, ECE, M.S. 2017, First Job: Power Management Firmware Developer, Intel
- Arjun Pal Chowdhury, CS, M.S. 2017, First Job: Principal Design Engineer, NXP
- Yomi Karthik Rupesh, ECE, M.S. 2018, First Job: SoC Design Engineer, NVIDIA
- Payman Behnam, CS, M.S. 2020, First Job: PhD Student, Georgia Institute of Technology
- Venkatrajreddy Sunkari, ECE, M.S. 2020, First Job: Senior Design Engineer, Infineon Technologies
- Ananth Krishna Prasad, CS, Ph.D. 2024, First Job: Senior Engineer, Qualcomm
Professional Activities
- Editorial Board: Microelectronics Journal
- Organizing Committee: ISCA'17 (Publications Chair)
- Program Committee: IPDPS'17, ICPP'17, ICCD'17, EMC2'18 (with ASPLOS), ICCD'18-20, HPCA'19, DAC'20
- External Review Committee: HPCA'16, HPCA'18, DAC'18, MICRO'20
- Panel: National Science Foundation
Book Chapters
- Emerging Hardware Technologies for IoT Data Processing, Mahdi Nazm Bojnordi, Payman Behnam, Springer International Publishing, Cham, 2020.
- The Smart "Things" in IoT, Farshad Firouzi, Bahar Farahani, Mahdi Nazm Bojnordi, Springer International Publishing, Cham, 2020.
Patents
- Superconducting System Architecture for High-Performance Energy-Efficienct Cryogenic Computing, US Patent Number 2019/0188596
- Application Defined Computing Component Configuration, US Patent Number 2014/0108773
- Programmable Memory Controller, US Patent Number 2013/0282972